UK's Hardware Sensing Δ 15th of May 2017 Ω 5:03 PM

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~ Malvern ~ MultiCore Information ~ Linux	~ picoChip ~ API Technologies ~ Cambridge Graphene Centre	~ Plastic Logic ~ ARM ~ sense for Ξ
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«Hardware Sensing	Θ	Θ
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~ Malvern

»Mastersizer particle size analyzers
ξ Jet Engines

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~ MultiCore Information

»MultiCore Information

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~ Linux

»Linux
»Python 3.0 makes a big break

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~ picoChip

picoChip

Multicore DSP
ξ picoChip’s multi-core DSPs deliver dramatically better performance-per-dollar and performance-per-Watt
ξ than traditional DSP or FPGA architectures, in an easy to program manner
ξ picoArray architecture integrates over 300 processors on a single chip,
ξ delivering far better performance than is attainable with traditional DSPs
ξ picoArray is programmed using a familiar development environment in ANSI C or simple assembler
ξ communications systems designers can use a single chip to implement fast datapath functions like
ξ FFTs, filtering and correlation, seamlessly integrated with complex control operations such as channel estimation and adaption
ξ delivering 200GIPS & 30 GMACS at 160MHz, the picoArray is already in use in the wireless infrastructure of dozens of carriers worldwide
ξ PC102 delivers 40-times better performance-per-dollar than legacy DSP architectures
ξ picoArray is the first (and currently only) production multi-core DSP to have been subjected to such a performance audit
ξ the first processors to overcome the $1/GMAC barrier, the devices include an optional ARM9 processor core, and
ξ application-specific acceleration blocks
ξ these enable PHY, MAC and protocol stack to be integrated in a single device,
ξ enabling cost-effective systems for applications such as femtocells and 4G base-stations
ξ picoArray benchmarks at 395 ByteGigaOperations per second (ByteGOPS),
ξ some three times higher than its nearest rival and yet running at a clock speed of just 160MHz
ξ the use of multi-core technology gives the designer access to even higher levels of performance than can be achieved with a single chip
ξ picoArray architecture scales easily, permitting multiple devices to be used to address even more demanding applications,
ξ while retaining a consistent design philosophy and programming architecture

Multi-core DSP Chips for Next-gen Wireless
ξ picoChip launched its next generation of picoArray multi-core processor arrays for next-generation wireless systems
ξ PC202, PC203 and PC205 are the first devices in the family
ξ are highly integrated, high-performance and extremely cost-effective DSPs
ξ they all integrate around 200 or more individual processors onto each die and deliver over 100GIPs and 25GMACs
ξ dramatically better performance than legacy single-core DSPs
ξ pricing from just $25 in high volume
ξ achieves the '$1 per GMAC' metric, enabling unprecedented performance at consumer price-points
ξ PC202 and 205 also integrate a powerful ARM9 processor
ξ all three products are programmed in standard C or assembler
ξ making them suited to complete software radio systems, and
ξ full reference designs are available for WiMAX (both 16d and 16e) and WCDMA (including HSDPA, with upgrade to HSUPA)
ξ PC202 integrates 198 individual DSPs, as well as an ARM 926EJ-S for control and MAC functionality, and
ξ is intended for cost-critical applications such as WiMAX client side systems and access points, and WCDMA femtocells (home basestations)
ξ PC203 has 248 individual processors and is designed for basestation (BS) applications
ξ where it can support popular wireless communication protocols such as WiMAX and HSDPA/HSUPA,
ξ including support for advanced algorithms such as MIMO and beamforming
ξ it is used with an external control processor or network processor in large basestations
ξ PC205 has 248 individual DSPs, and in addition includes a powerful ARM 926EJ-S
ξ it is intended for higher-performance stand-alone applications including software-defined radios and high-performance backhaul or mesh nodes
ξ ARM processor is used for all higher MAC and basestation control tasks, dramatically reducing bill-of-materials
ξ all three chips feature a cryptographic engine, and
ξ optimized co-processors for FFT/IFFT, Viterbi and turbo decoders (including CTC for 16e)
ξ this functionality is all integrated into picoChip's interconnect fabric and development environment,
ξ making it very easy to program, integrate and verify
ξ the individual DSPs used in all three devices are backward-compatible with those used in picoChip's PC102 device,
ξ which has been shipping in volume for over a year
ξ this has enabled picoChip's customers to develop systems using PC102, and
ξ then benefit directly from the cost-savings provided by PC20x devices as soon as they are available
ξ each individual processor is a fully-featured DSP, including a 16x16-bit multiplier with 40-bit accumulators, local instruction and
ξ data memory, and uses a modified three-way Long Instruction Word (LIW) architecture
ξ a processor can execute a Multiply-Accumulate (MAC) instruction and up to three other instructions in the same cycle
ξ with 248 processors in PC203 and PC205, all running at 160 MHz,
ξ this adds up to nearly 160 GIPS even before specialist wireless accelerators for functions such as Turbo and Viterbi decoding and cryptography are taken into account
ξ picoChip provides software defined radio solutions to the key challenges of cost, development time and flexibility for the next generation of wireless systems
ξ multi-core processors deliver a world-beating price/performance combination
ξ picoChip has achieved design wins with numerous major companies
ξ company also delivers complete, standard-compliant reference designs for
ξ UMTS (HSDPA, upgradeable to HSUPA) and WiMAX/WiBRO (both 802.16d and 802.16e, with support for AAS and MIMO)
ξ WiMAX systems using picoChip are available from Airspan, Intel, Ericsson, Nortel, Marconi and a number of other manufacturers
ξ PC102 picoArray is also being used to develop other advanced wireless protocols such as 802.20 and TD-SCDMA, and in 4G research

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~ API Technologies

»API Technologies

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~ Cambridge Graphene Centre

»Cambridge Graphene Centre
investigates the science and technology of graphene, carbon allotropes, layered crystals and hybrid nanomaterials
allows its partners to meet, and effectively establish joint industrial-academic activities to promote innovative and adventurous research with an emphasis on applications

the facilities and equipment have been selected to promote alignment with industry, by filling two main vacuums
the first is the lack of intermediate scale printing and processing systems
where the industrial upscale and optimization of inks based on graphene, related carbon nanomaterials, and
novel two dimensional crystals can be tested and optimized

the second vacuum stems from the challenge posed by the unique properties of graphene:
the centre facilities aim to fully cover those properties necessary to achieve the goal of "graphene-augmented"
smart integrated devices on flexible/transparent substrates,
with the necessary energy storage capability to work autonomously and wireless connected

the strategic focus are activities built around the central challenge of flexible and energy efficient (opto)electronics,
for which graphene and related materials are a unique enabling platform
this will be achieved through four main themes:
T1: growth, transfer and printing
T2: energy
T3: connectivity
T4: detectors

the core funding to establish the Centre comes from two programme grants and
one equipment grant under the "EPSRC Graphene Engineering" call, from the Graphene Flagship, and
the ERC Synergy Grant Hetero2D

Within the ERC framework, the Cambridge Graphene Centre is part of a Synergy group with the Graphene National Institute in Manchester, and
the University of Lancaster, targeting heterostructures and superstructures
based on two-dimensional atomic crystals and their hybrids with metallic and semiconducting quantum dots

This new concept of "materials on demand" will enable a large number of different artificial three-dimensional materials,
with tailored properties, to be used in new multifunctional devices

Research Associate in Modelling of Graphene and Related Materials
to work on theoretical modelling of graphene and related materials (GRMs)
the project is funded by the European Research Council, and based at the Cambridge Graphene Centre (CGC)
the successful candidate will provide theoretical support, via numerical simulations, to complement the CGC experimental activities,
in addition to working on more fundamental projects in collaboration with leading national and international theoretical groups and in the context of the Graphene Flagship
possible projects include the interpretation and modelling of Raman spectra, the theory of non-linear optics, as well as band structure and phonon calculations
the successful candidate will have a PhD in Physics, Materials Science, Nanotechnology, Chemistry or Electrical Engineering, and
a proven expertise in the modelling of electronic, vibrational and optical properties of materials using density-functional theory-based methods,
as well as a deep knowledge of scientific programming, as demonstrated by publications in major international journals and presentations in major conferences
a solid understanding of the physics of GRMs is required, as well as an excellent understanding of Raman spectroscopy
experience of beyond-DFT methods (GW, BSE) is highly desirable

Flexible Display
The partnership between the two organisations combines the graphene expertise of the Cambridge Graphene Centre (CGC),
with the transistor and display processing steps that Plastic Logic has already developed for flexible electronics.
This prototype is a first example of how the partnership will accelerate the commercial development of graphene.
It is a first step towards the wider implementation of graphene and graphene-like materials into flexible electronics.

Graphene is a two-dimensional material made up of sheets of carbon atoms.
It is among the strongest, most lightweight and flexible materials known, and has the potential to revolutionise industries from healthcare to electronics.

The new prototype is an active matrix electrophoretic display,
similar to the screens used in today’s e-readers, except it is made of flexible plastic instead of glass.

In contrast to conventional displays, the pixel electronics, or backplane, of this display
includes a solution-processed graphene electrode, which replaces the sputtered metal electrode layer within Plastic Logic’s conventional devices, bringing product and process benefits.

Graphene is more flexible than conventional ceramic alternatives like indium-tin oxide (ITO) and more transparent than metal films.
The ultra-flexible graphene layer may enable a wide range of products, including foldable electronics.
Graphene can also be processed from solution bringing inherent benefits of using more efficient printed and roll-to-roll manufacturing approaches.

The new 150 pixel per inch (150 ppi) backplane was made at low temperatures (less than 100°C)
using Plastic Logic’s Organic Thin Film Transistor (OTFT) technology.
The graphene electrode was deposited from solution and subsequently patterned with micron-scale features to complete the backplane.

For this prototype, the backplane was combined with an electrophoretic imaging film to create an ultra-low power and durable display.
Future demonstrations may incorporate liquid crystal (LCD) and organic light emitting diodes (OLED) technology
to achieve full colour and video functionality.

Lightweight flexible active-matrix backplanes may also be used for sensors,
with novel digital medical imaging and gesture recognition applications already in development.

“We are happy to see our collaboration with Plastic Logic resulting in the first graphene-based electrophoretic display exploiting graphene in its pixels’ electronics,”
said Professor Andrea Ferrari, Director of the Cambridge Graphene Centre.
“This is a significant step forward to enable fully wearable and flexible devices.
This cements the Cambridge graphene-technology cluster and shows how an effective academic-industrial partnership is key to help move graphene from the lab to the factory floor.”

“The potential of graphene is well-known, but industrial process engineering is now required to transition graphene from laboratories to industry,”
said Indro Mukerjee, CEO of Plastic Logic.
“This demonstration puts Plastic Logic at the forefront of this development,
which will soon enable a new generation of ultra-flexible and even foldable electronics”

This joint effort between Plastic Logic and the CGC was also recently boosted by a grant from the UK Technology Strategy Board,
within the ‘realising the graphene revolution’ initiative.
This will target the realisation of an advanced, full colour, OELD based display within the next 12 months.

The project is funded by the Engineering and Physical Sciences Research Council (EPSRC) and the EU’s Graphene Flagship.

»Andrea Ferrari
The main NMS research areas combine growth, characterisation and device assembly.
In particular, we work on growth and characterization of diamond-like carbon, graphene, carbon nanotubes, and
semiconductor nanowires for coating, optoelectronics and sensing applications.
A strong focus on the non-linear optical properties of nanotubes for applications in photonic devices.
Pursues the non-destructive characterization of carbon films,
devising innovative ways to probe their structure and
tailor it to get better mechanical, optical and electronic properties.
Has a leading activity on the application of Raman spectroscopy to carbon films and nanomaterials.
All experimental work is paralleled by first principles calculations and modeling.
Have a comprehensive approach to nanotechnology:
can design and grow new materials, characterize them, implement them into devices and
investigate their fundamental properties. We have several projects funded by the EPSRC, the Royal Society, Europe, The Newton and Leverhulme trusts, and we enjoy close collaborations with several companies.

»Plastic Logic

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~ Plastic Logic

»Plastic Logic

Plastic Logic
is the leader in the field of plastic electronics
founded by researchers from the Cavendish Laboratory at Cambridge University
has been at the forefront of research and investment into plastic electronics
has achieved many technological firsts in making plastic electronics a reality
was the first to fully industrialise the mass production of plastic electronics
in the world's first plastic electronics factory, achieving production yields of plastic electronic displays comparable to the LCD industry
has broken new ground with what is possible with plastic electronic displays
develops and manufactures ultra-thin, ultra-lightweight and high-quality plastic displays of various sizes and in both colour and monochrome
these plastic displays offer huge advantages over conventional screens being extremely flexible and
hard-wearing with proven lifetimes of over five years and more than ten million page updates
leverages its R&D and manufacturing resources to allow partners such as OEMs, system integrators and device manufacturers, to utilise its flexible display technology
has an established footprint in the UK, Germany and Russia
sells globally
is supported by a broad and experienced international investor base
is backed by major investors including Oak Investment Partners and Rusnano
»RUSNANO

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~ ARM

»ARM

ARM DynamIQ: Expanding the possibilities for artificial intelligence
ξ 100 billion ARM-based chips
ξ 50 billion shipped by ARM partners from 2013 to 2017
ξ demonstrates the industry’s insatiable demand for more compute
ξ ARM expects its partners to ship the next 100 billion ARM-based chips by 2021
ξ demand for ubiquitous AI, autonomous systems and accelerating the integration of virtual worlds toward a mixed reality experience

The next phase of ARM Cortex-A processors
ξ an evolutionary step forward for ARM big.LITTLE technology
ξ to revolutionized multi-core characteristics
ξ carries on the ‘right processor for the right task’ approach
ξ enables configurations of big and LITTLE processors on a single compute cluster which were previously not possible
ξ for example, 1+3 or 1+7 DynamIQ big.LITTLE configurations with substantially more granular and optimal control are possible
ξ boosts innovation in SoCs designed with right-sized compute with heterogeneous processing
ξ that deliver meaningful AI performance at the device itself

New dedicated processor instructions for ML and AI
ξ specialized accelerator hardware on the SoC

Increased multi-core flexibility
ξ SoC designers can scale up to eight cores in a single cluster
ξ each core can have different performance and power characteristics
ξ enable faster responsiveness to ML and AI applications
ξ redesigned memory subsystem enables both faster data access and enhance power management

More performance within restricted thermal budgets
ξ efficient and much faster switching of software tasks
ξ to match the right-sized processor for optimal performance and
ξ power is further enhanced through independent frequency control of individual processors

Safer autonomous systems
ξ greater levels of responsiveness for ADAS solution
ξ increased safety capabilities

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