Reconfigurable Computing
~ a hardware object is a functional or logical hardware component that contains its own configuration and state information
~ it is a piece of logic that can be executed in an RPU (Reconfigurable Processing Unit)
~ hardware objects are position-independent, or relocatable, to allow to execute them from any convenient and available position within chip
~ it is desirable to add constraints on their size and shape
~ these constraints limit the number of possible positions within the FPGA and make run-time decision-making more efficient and effective
~ actual constraints should be based on the features of a particular FPGA or FPGA family
~ the best constraints require that all hardware objects be rectangular in shape and have edge lengths that are multiples of some unit length
~ called the hardware page size, which may be any convenient number of gates
~ for example, page sizes of 4 and 16 gates work very well for Xilinx 62xx series FPGAs
~ because these parts have additional routing resources at each of those intersections,
~ which makes routing between hardware objects or a hardware object and its I/O pins much easier
~ second, it is desirable to define a standard look and feel for hardware object interfaces
~ idea is to make interobject routing easier by defining standard interfaces between them
~ this is especially important if routing between objects will be performed on-the-fly,
~ and it also paves way for greater hardware object re-use
~ by standardizing interfaces of all hardware objects, it is possible to maintain libraries of frequently used objects
~ and to quickly build larger designs from these smaller components
~ in some cases, it may even be possible to purchase third-party hardware objects rather than designing your own
~ assume that any hardware objects that expect to interface to world outside
~ RPU (to a block of memory, the processor, a peripheral, or even another RPU) must do so through an abstraction
~ this abstraction is called the hardware object framework, which is a ring of logic
~ that is always present within the RPU and physically located along outer edges
~ framework provides a set of standard interfaces to memory and peripheral devices located outside of the RPU
~ this ring of logic shrinks available space for executing hardware objects,
~ but that is a small price to pay for greater hardware object re-usability and, hence, faster design cycles
»Microship Technologies
»Esutech

Related terms(s)
»Reconfigurable_Hardware